Neuromorphic hardware accelerator for SNN inference based on STT-RAM crossbar arrays

Document Type

Conference Proceeding

Publication Date

11-1-2019

Abstract

In this paper, we propose a Spin Transfer Torque RAM (STT-RAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the time-based signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of non-volatile STT-RAMs, read/write peripheral circuits, and digital logic for the spiking neurons. Inter-core communication is realized through on-chip routing network by sending/receiving spike packets. Unlike prior works that use multi-level states of non-volatile memory (NVM) devices for the synaptic weights, we use the technologically-mature STT-RAM devices for binary data storage. The design studies are conducted using a compact model for STT-RAM devices, tuned to capture the state-of-the-art experimental results. Our design avoids the need for expensive ADCs and DACs, enabling instantiation of large NVM arrays for our core. We show that the STT-RAM based neurosynaptic core designed in 28 nm technology node has approximately 6× higher throughput per unit Watt and unit area than an equivalent SRAM based design. Our design also achieves ∼ 2× higher performance per Watt compared to other memristive neural network accelerator designs in the literature.

Identifier

85079196851 (Scopus)

ISBN

[9781728109961]

Publication Title

2019 26th IEEE International Conference on Electronics Circuits and Systems Icecs 2019

External Full Text Location

https://doi.org/10.1109/ICECS46596.2019.8964886

First Page

438

Last Page

441

Grant

2016-SD-2717

Fund Ref

Semiconductor Research Corporation

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