Enabling Normally-Off in Situ Computing with a Magneto-Electric FET-Based SRAM Design

Document Type

Article

Publication Date

4-1-2024

Abstract

As an emerging post-CMOS Field Effect Transistor, magneto-electric field-effect transistors (MEFETs) offer compelling design characteristics for logic and memory applications, such as high-speed switching, low power consumption, and nonvolatility. In this article, for the first time, a nonvolatile MEFET-based SRAM design named ME-SRAM is proposed for edge applications which can remarkably save the SRAM static power consumption in the idle state through a fast backup-restore process. To enable normally- OFF in situ computing, the ME-SRAM cell is integrated into a novel processing-in-SRAM architecture that exploits a hardware-optimized bitline computing approach for the execution of Boolean logic operations between operands housed in a memory sub-array within a single clock cycle. Our device-to-architecture evaluation results on Binary convolutional neural network acceleration show the robust performance of ME-SRAM while reducing energy consumption on average by a factor of compared to the best in-SRAM designs.

Identifier

85186068403 (Scopus)

Publication Title

IEEE Transactions on Electron Devices

External Full Text Location

https://doi.org/10.1109/TED.2024.3366172

e-ISSN

15579646

ISSN

00189383

First Page

2742

Last Page

2748

Issue

4

Volume

71

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