Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing

Document Type

Conference Proceeding

Publication Date

6-12-2024

Abstract

The surge in the number of normally-off power-constraint Internet of Things (IoT) devices in recent years has amplified the demand for high-performance and energy-efficient in-memory computing architectures built on top of various non-volatile memories. Magneto-Electric Field Effect Transistors (MEFETs) have presented compelling design features suitable for logic and memory integration as an emerging post-CMOS FET. These include high-speed switching, minimal power usage, and non-volatility. This work introduces a new in-memory computing architecture designed for edge applications, leveraging emerging MEFETs. The proposed architecture enables the execution of both Boolean logic operations and Binary Content Addressable Memory (BCAM) operations within a single cycle. Furthermore, the energy consumption during the write operation of the proposed cell is optimized by introducing a new write circuitry. The outcomes of our device-to-architecture evaluation reveal approximately 43.5% and 96.9% reduction in read and write energy consumption, respectively, compared to the counterpart non-volatile memories. At the application level, the proposed architecture is applied to implement Binary Neural Networks (BNNs) based on AlexNet and VGG16. Our results showcase a decrease of approximately 54% in the overall energy consumption when implementing these networks using the proposed design compared to non-volatile in-memory computing designs.

Identifier

85197948535 (Scopus)

ISBN

[9798400706059]

Publication Title

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

External Full Text Location

https://doi.org/10.1145/3649476.3660361

First Page

770

Last Page

775

Grant

2228028

Fund Ref

National Science Foundation

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