ReD-LUT: Reconfigurable in-DRAM LUTs enabling massive parallel computation
Document Type
Conference Proceeding
Publication Date
10-30-2022
Abstract
In this paper, we propose a reconfigurable processing-in-DRAM architecture named ReD-LUT leveraging the high density of commodity main memory to enable a flexible, general-purpose, and massively parallel computation. ReD-LUT supports lookup table (LUT) queries to efficiently execute complex arithmetic operations (e.g., multiplication, division, etc.) via only memory read operation. In addition, ReD-LUT enables bulk bit-wise in-memory logic by elevating the analog operation of the DRAM sub-array to implement Boolean functions between operands stored in the same bit-line beyond the scope of prior DRAM-based proposals. We explore the efficacy of ReD-LUT in two computationally-intensive applications, i.e., low-precision deep learning acceleration, and the Advanced Encryption Standard (AES) computation. Our circuit-to-architecture simulation results showthat for a quantized deep learningworkload, ReD-LUT reduces the energy consumption per image by a factor of 21.4× compared with the GPU and achieves ∼37.8× speedup and 2.1× energy-efficiency over the best in-DRAM bit-wise accelerators. As for AES data-encryption, it reduces energy consumption by a factor of ∼2.2× compared to an ASIC implementation.
Identifier
85144245602 (Scopus)
ISBN
[9781450392174]
Publication Title
IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad
External Full Text Location
https://doi.org/10.1145/3508352.3549469
ISSN
10923152
Grant
1710009
Fund Ref
National Science Foundation
Recommended Citation
Zhou, Ranyang; Roohi, Arman; Misra, Durga; and Angizi, Shaahin, "ReD-LUT: Reconfigurable in-DRAM LUTs enabling massive parallel computation" (2022). Faculty Publications. 2575.
https://digitalcommons.njit.edu/fac_pubs/2575
