Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges

Document Type

Conference Proceeding

Publication Date

1-1-2023

Abstract

Digital Processing-in-Memory (PIM) architectures have recently unleashed significant potential in Deep Neural Network (DNN) acceleration not only by addressing memory-wall bottlenecks but also by offering impressive performance improvement compared to the von-Neumann architecture. Different flavors of DNN ASIC accelerators have also been developed and fabricated, with remarkable performance and efficiency. This paper conducts a comparative study of PIM and Gemmini-generated accelerators for low-bit-width DNN inference and underscores their key architectural constraints, opportunities, and security challenges. To this end, we compare multiple low-power accelerators with our recently taped-out PIM macro to provide a guideline for the community.

Identifier

85185371324 (Scopus)

ISBN

[9798350302103]

Publication Title

Midwest Symposium on Circuits and Systems

External Full Text Location

https://doi.org/10.1109/MWSCAS57524.2023.10405996

ISSN

15483746

First Page

797

Last Page

800

Grant

2216772

Fund Ref

National Science Foundation

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