How to reduce aliasing in linear analog testing

Document Type

Conference Proceeding

Publication Date

1-1-2004

Abstract

Aliasing is a difficult problem that needs to be handled carefully, due to its effects on the test quality of analog circuits. In this paper, we first give the evidence of aliasing occurrence in the summation-based method, and then propose the concept of bound curve and derive the bound equation for finding the aliasing-reduced region and we present a case study of how to reduce aliasing. Finally we expand the aliasing study to obtain an optimal sampling frequency.

Identifier

2942696861 (Scopus)

ISBN

[1581138539, 9781581138535]

Publication Title

Proceedings of the ACM Great Lakes Symposium on VLSI

External Full Text Location

https://doi.org/10.1145/988952.989041

First Page

368

Last Page

371

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