Scan latch design for test applications

Document Type

Article

Publication Date

4-1-2004

Abstract

This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Identifier

3543107787 (Scopus)

Publication Title

Journal of Electronic Testing Theory and Applications JETTA

External Full Text Location

https://doi.org/10.1023/B:JETT.0000023683.62501.ed

ISSN

09238174

First Page

213

Last Page

216

Issue

2

Volume

20

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