Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths

Document Type

Article

Publication Date

1-1-2005

Abstract

This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

Identifier

26044452392 (Scopus)

Publication Title

IEICE Transactions on Information and Systems

External Full Text Location

https://doi.org/10.1093/ietisy/e88-d.8.1940

e-ISSN

17451361

ISSN

09168532

First Page

1940

Last Page

1946

Issue

8

Volume

E88-D

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