Defect level vs. yield and fault coverage in the presence of an unreliable BIST

Document Type

Article

Publication Date

1-1-2005

Abstract

Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

Identifier

25844439606 (Scopus)

Publication Title

IEICE Transactions on Information and Systems

External Full Text Location

https://doi.org/10.1093/ietisy/e88-d.6.1210

e-ISSN

17451361

ISSN

09168532

First Page

1210

Last Page

1216

Issue

6

Volume

E88-D

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