Load-balanced combined input-crosspoint buffered packet switch and long round-trip times

Authors

Roberto Rojas-Cessa, Newark College of Engineering
Ziqian Dong, Newark College of Engineering
Zhen Guo, Newark College of Engineering

Document Type

Article

Publication Date

1-1-2005

Abstract

The amount of memory in buffered crossbars is proportional to the number of crosspoints, or O(N²), where N is the number of ports, and to the crosspoint buffer size, which is defined by the distance between the line cards and the buffered crossbar, to achieve 100% throughput under high-speed data flows. A long distance between these two components can make a buffered crossbar costly to implement. In this letter, we propose a load-balanced combined input-crosspoint buffered packet switch that uses small crosspoint buffers and no speedup. The proposed switch reduces the required size of the crosspoint buffers by a factor of N and keeps the cells in sequence. © 2005 IEEE.

Identifier

23144462258 (Scopus)

Publication Title

IEEE Communications Letters

External Full Text Location

https://doi.org/10.1109/LCOMM.2005.1461697

ISSN

10897798

First Page

661

Last Page

663

Issue

7

Volume

9

Grant

0423305

Fund Ref

National Science Foundation

Recommended Citation

Rojas-Cessa, Roberto; Dong, Ziqian; and Guo, Zhen, "Load-balanced combined input-crosspoint buffered packet switch and long round-trip times" (2005). Faculty Publications. 19875.
https://digitalcommons.njit.edu/fac_pubs/19875