Optimizing the thermal behavior of subarrayed data caches

Document Type

Conference Proceeding

Publication Date

12-1-2005

Abstract

Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density. Extremely high power density, thus the very high on-chip temperature, not only significantly increases the packaging and cooling costs, but also creates tremendous difficulties in chip leakage control and reliability. Being a major contributor to chip transistor budget and die area, caches account for a significant share of the overall processor power consumption, including both dynamic and leakage power. This work analyzes the thermal behavior of subarrays within a conventional data cache when running a set of applications from the SPEC2000 benchmark suite, and proposes two new subarraying schemes, namely, the separated scheme and the interleaved scheme, to improve the thermal behavior of subarrays in terms of more predictable behavior and reduced subarray temperatures. These optimizations can be also combined with dynamic thermal management (DTM) techniques to further improve the efficiency of thermal management. The impact of leakage control on the subarray thermal behavior is also evaluated. © 2005 IEEE.

Identifier

33748524497 (Scopus)

ISBN

[0769524516, 9780769524511]

Publication Title

Proceedings IEEE International Conference on Computer Design VLSI in Computers and Processors

External Full Text Location

https://doi.org/10.1109/ICCD.2005.81

ISSN

10636404

First Page

625

Last Page

630

Volume

2005

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