A coarse-grain hierarchical technique for 2-dimensional FFT on configurable parallel computers
Document Type
Article
Publication Date
1-1-2006
Abstract
FPGAs (Field-Programmable Gate Arrays) have been widely used as coprocessors to boost the performance of data-intensive applications [1], [2]. However, there are several challenges to further boost FPGA performance: the communication overhead between the host workstation and the FPGAs can be substantial; large-scale applications cannot fit in a single FPGA because of its limited capacity; mapping an application algorithm to FPGAs still remains a daunting job in configurable system design. To circumvent these problems, we propose in this paper the FPGA-based Hierarchical-SIMD (H-SIMD) machine with its codesign of the Pyramidal Instruction Set Architecture (PISA). PISA comprises high-level instructions implemented as FPGA functions of coarse-grain SIMD (Single-Instruction, Multiple-Data) tasks to facilitate ease of program development, code portability across different H-SIMD implementations and high performance. We assume a multi-FPGA board where each FPGA is configured as a separate SIMD machine. Multiple FPGA chips can work in unison at a higher SIMD level, if needed, controlled by the host. Additionally, by using a memory switching scheme and the high-level PISA to partition applications into coarse-grain tasks, host-FPGA communication overheads can be hidden. We enlist the two-dimensional Fast Fourier Transform (2D FFT) to test the effectiveness of H-SIMD. The test results show sustained high performance for this problem. The H-SIMD machine even outperforms a Xeon processor for this problem. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.
Identifier
33645231859 (Scopus)
Publication Title
IEICE Transactions on Information and Systems
External Full Text Location
https://doi.org/10.1093/ietisy/e89-d.2.639
e-ISSN
17451361
ISSN
09168532
First Page
639
Last Page
645
Issue
2
Volume
E89-D
Recommended Citation
Xu, Xizhen and Ziavras, Sotirios G., "A coarse-grain hierarchical technique for 2-dimensional FFT on configurable parallel computers" (2006). Faculty Publications. 19126.
https://digitalcommons.njit.edu/fac_pubs/19126
