A switcher ASIC design for use in a charge-pump detector

Document Type

Article

Publication Date

12-26-2012

Abstract

The objective of this paper is to describe a Switcher ASIC with 64 high voltage output channels. Each channel provides two high voltage control pulses with maximum amplitudes of 32 V. The high voltage level shifter was designed with a current mirror switching circuit that has a readily adjustable switching speed, unlike conventional switching circuits. The logic control circuit uses a forward and reverse chain of Flip-Flops along with other combinational logic gates to generate bidirection sequential control pulses with adjustable pulsewidth and polarity. The layout was carefully designed to achieve a 14 μ m width for the last stage transistors' drain path based on the 50 μm output channel pitch set up. At least a 200 mA current driving capability was obtained for each channel. The design was fabricated using TSMC's 180 nm CMOS HV technology. The paper further discusses the critical design steps including chip architecture, layout, simulation and bench test. The final experimental results demonstrate that the Switcher ASIC meets requirements and the rising time could reach 480 ns with a 1 nF capacitive load at 15 V pulse amplitude. With this load, the total power consumption of the chip was measured to be approximately 4 mW when the input clock period was 42.2 μs. In addition to use in a charge-pump detector, the ASIC can be used to control the charge accumulation and readout in other detectors, such as X-ray pump probe detectors (XPP). © 1963-2012 IEEE.

Identifier

84871386724 (Scopus)

Publication Title

IEEE Transactions on Nuclear Science

External Full Text Location

https://doi.org/10.1109/TNS.2012.2215883

ISSN

00189499

First Page

3205

Last Page

3212

Issue

6

Volume

59

Grant

DMR 0722730

Fund Ref

National Science Foundation

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