Delay Test Generation: A Hardware Perspective

Document Type

Article

Publication Date

1-1-1997

Abstract

An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions on the kind of hardware suitable for the task, especially in built-in self-test applications where the generator must reside on chip. This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. The different options are measured based on their performance, cost, and flexibility.

Identifier

0031166993 (Scopus)

Publication Title

Journal of Electronic Testing Theory and Applications JETTA

External Full Text Location

https://doi.org/10.1023/A:1008219725676

ISSN

09238174

First Page

245

Last Page

254

Issue

3

Volume

10

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