Module Level Weighted Random Patterns

Document Type

Article

Publication Date

1-1-1997

Abstract

The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signature is collected by a multiple input signature register (MISR). Each scan latch in the module is fed by its near-optimal weight during test. In order to avoid any additional test pins, some of the existing signal pins are designated (demultiplexed) to perform a weight control function during test. This architecture can dramatically decrease the self-test time with only a small increase of hardware overhead.

Identifier

0031163939 (Scopus)

Publication Title

Journal of Electronic Testing Theory and Applications JETTA

External Full Text Location

https://doi.org/10.1023/A:1008227927494

ISSN

09238174

First Page

283

Last Page

287

Issue

3

Volume

10

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