A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

Authors

Krishnaswamy Nagaraj, IEEE
H. Scott Fetterman, Nokia Corporation
Joseph Anidjar, Nokia Corporation
Stephen H. Lewis, IEEE
Robert G. Renninger, Nokia Corporation

Document Type

Article

Publication Date

3-1-1997

Abstract

A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a 52 Msamples/s prototype A/D converter that is intended for a switched digital video application has been implemented in a 0.9-μm CMOS technology. The device occupies 15 mm ² and dissipates 250 mW from a 5 V supply.

Identifier

0031102957 (Scopus)

Publication Title

IEEE Journal of Solid State Circuits

External Full Text Location

https://doi.org/10.1109/4.557628

ISSN

00189200

First Page

312

Last Page

320

Issue

3

Volume

32

Recommended Citation

Nagaraj, Krishnaswamy; Fetterman, H. Scott; Anidjar, Joseph; Lewis, Stephen H.; and Renninger, Robert G., "A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers" (1997). Faculty Publications. 16736.
https://digitalcommons.njit.edu/fac_pubs/16736