SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP

Document Type

Conference Proceeding

Publication Date

6-5-2023

Abstract

Recently, Intelligent IoT (IIoT), including various sensors, has gained significant attention due to its capability of sensing, deciding, and acting by leveraging artificial neural networks (ANN). Nevertheless, to achieve acceptable accuracy and high performance in visual systems, a power-delay-efficient architecture is required. In this paper, we propose an ultra-low-power processing in-sensor architecture, namely SenTer, realizing low-precision ternary multi-layer perceptron networks, which can operate in detection and classification modes. Moreover, SenTer supports two activation functions based on user needs and the desired accuracy-energy trade-off. SenTer is capable of performing all the required computations for the MLP's first layer in the analog domain and then submitting its results to a co-processor. Therefore, SenTer significantly reduces the overhead of analog buffers, data conversion, and transmission power consumption by using only one ADC. Additionally, our simulation results demonstrate acceptable accuracy on various datasets compared to the full precision models.

Identifier

85163180170 (Scopus)

ISBN

[9798400701252]

Publication Title

Proceedings of the ACM Great Lakes Symposium on VLSI Glsvlsi

External Full Text Location

https://doi.org/10.1145/3583781.3590225

First Page

497

Last Page

502

Grant

2216772

Fund Ref

National Science Foundation

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