Random pattern testability of memory control logic

Document Type

Article

Publication Date

1-1-1998

Abstract

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary. © 1998 IEEE.

Identifier

0032023485 (Scopus)

Publication Title

IEEE Transactions on Computers

External Full Text Location

https://doi.org/10.1109/12.660166

ISSN

00189340

First Page

305

Last Page

312

Issue

3

Volume

47

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