Random pattern testability of memory address logic

Document Type

Article

Publication Date

12-1-1998

Abstract

An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the address inputs of embedded memories. Difference information from replicated copies of embedding logic is used to determine the probability of detecting any fault in the upstream of either a read or write port address decoder. The method can be used with minor extensions to existing detection probability tools such as the cutting algorithm. © 1998 IEEE.

Identifier

0343212169 (Scopus)

Publication Title

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems

External Full Text Location

https://doi.org/10.1109/43.736570

ISSN

02780070

First Page

1310

Last Page

1318

Issue

12

Volume

17

Fund Ref

Nanjing Institute of Technology

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