BIST diagnostics, Part 1: Simulation models

Document Type

Conference Proceeding

Publication Date

12-1-1998

Abstract

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The idea is to create simulation models that only use the combinational logic (i.e., the memory is removed).

Identifier

0032305515 (Scopus)

Publication Title

Proceedings of the Asian Test Symposium

ISSN

10817735

First Page

8

Last Page

14

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