Concurrency preserving partitioning algorithm for parallel logic simulation

Document Type

Article

Publication Date

1-1-1999

Abstract

A partitioning algorithm for parallel discrete event gate-level logic simulations is described. This algorithm preserves computation concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the improved concurrency preserving partitioning (iCPP) algorithm can provide better load balancing throughout the period of parallel simulation. The performance of the icpp algorithm is evaluated by implementing a parallel gate-level logic simulator on an INTEL Paragon and an IBM SP2. Comparison of the results to several other partitioning algorithms show that the iCPP algorithm does preserve concurrency pretty well and reasonable speedup may be achieved with the algorithm.

Identifier

0032665642 (Scopus)

Publication Title

VLSI Design

External Full Text Location

https://doi.org/10.1155/1999/18373

ISSN

1065514X

First Page

253

Last Page

270

Issue

3

Volume

9

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