Electrical characterization of a double barrier direct tunneling diode structure

Document Type

Conference Proceeding

Publication Date

1-1-1999

Abstract

We report the electrical characterization of a direct tunneling diode structure that incorporates a multilayer dielectric. The dielectric consists of a stack of two thermally grown, ultrathin SiO2 layers, each approx. 3.5 nm thick, separated by a deposited, continuous, undoped, ultrathin nanocrystalline Si layer approx. 5.0 nm thick. Electrical measurements of this structure are reported for both n-type and p-type Si substrates. We find that the room temperature transport through this structure is accounted for by describing the intermediate Si layer as a quantum well with a continuum of states, and by otherwise assuming bulk properties for the ultrathin layers, such as the existence of a bandgap in the Si well and the usual Si-SiO2 interface potential barrier height at all interfaces. This structure is expected to be useful as the active dielectric in nonvolatile memory devices.

Identifier

0033350824 (Scopus)

Publication Title

Materials Research Society Symposium Proceedings

External Full Text Location

https://doi.org/10.1557/proc-567-247

ISSN

02729172

First Page

247

Last Page

252

Volume

567

Grant

9624798

Fund Ref

National Science Foundation

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