Design for testability to combat delay faults

Document Type

Article

Publication Date

12-1-1999

Abstract

To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips.

Identifier

0033297895 (Scopus)

Publication Title

Proceedings IEEE International Conference on Computer Design VLSI in Computers and Processors

First Page

407

Last Page

411

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