Impact of gate-poly grain structure on the gate-oxide reliability

Document Type

Article

Publication Date

1-1-2002

Abstract

Time dependent dielectric breakdown of thin oxides, 1.5 to 5.0 nm has been studied for different gate-poly grain structures. The poly grain was varied by the poly deposition, and the source-drain (S/D) rapid thermal anneal (RTA) conditions. The study, which was done on fully fabricated CMOS devices, showed substantial reliability degradation in thin gate oxides (below 2.0 nm), when using S/D RTA temperatures above 1000 °C. The results can be explained in terms of the interface roughness at the gate poly interface induced by the S/D RTA temperature above the viscoelastic point of the SiO2. A possible mechanism for the drastic reliability degradation in thin gate oxides, is the protrusion of poly grains into the softening oxide at high temperature.

Identifier

0036166125 (Scopus)

Publication Title

IEEE Electron Device Letters

External Full Text Location

https://doi.org/10.1109/55.974800

ISSN

07413106

First Page

22

Last Page

24

Issue

1

Volume

23

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