Ultra low power CMOS PLL clock synthesizer for wireless sensor nodes
Document Type
Conference Proceeding
Publication Date
1-1-2007
Abstract
This paper describes the design of an ultra low power CMOS PLL clock synthesizer targeting wireless sensor applications that require a low minimum power dissipation. Based on an integer-N architecture, the PLL clock synthesizer produces a 100 kHz output signal from a reference input signal generated using an on-chip crystal oscillator operating at 32.768 kHz. Fabricated in a 0.6-μm N-well CMOS process technology, the PLL achieves a power consumption of 20 μW with a frequency accuracy of ±13 Hz. © 2007 IEEE.
Identifier
34548819057 (Scopus)
Publication Title
Proceedings IEEE International Symposium on Circuits and Systems
External Full Text Location
https://doi.org/10.1109/iscas.2007.378054
ISSN
02714310
First Page
3059
Last Page
3062
Recommended Citation
Gundel, Adnan and Carr, William N., "Ultra low power CMOS PLL clock synthesizer for wireless sensor nodes" (2007). Faculty Publications. 13686.
https://digitalcommons.njit.edu/fac_pubs/13686
