Asymmetrically banked value-aware register files

Document Type

Conference Proceeding

Publication Date

11-28-2007

Abstract

Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined super-scalar microprocessors. In this paper, we propose a new microarchitecture, the asymmetrically-banked value-aware register file (AB-VARF), to exploit the prevailing narrow-width register values for low-latency and power-efficient register file designs. The register bit-widths of different banks in our AB-VARF register files are specifically customized to capture different narrow-width values. Augmented with a value width predictor, the register renaming logic is slightly tuned to rename predicted narrow-width registers to the corresponding narrow-width banks. Our experimental evaluation with SPEC CINT2000 benchmark suites shows that AB-VARF reduces the energy consumption by 92.6% over a conventional register file, on the average, at the cost of a 6.6% performance loss to an ideal 1-cycle monolithic register file. © 2007 IEEE.

Identifier

36349037023 (Scopus)

ISBN

[0769528961, 9780769528960]

Publication Title

Proceedings IEEE Computer Society Annual Symposium on VLSI Emerging VLSI Technologies and Architectures

External Full Text Location

https://doi.org/10.1109/ISVLSI.2007.27

First Page

363

Last Page

368

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