Asymmetrically banked value-aware register files for low-energy and high-performance

Document Type

Article

Publication Date

5-1-2008

Abstract

Designing high-performance low-energy register files is of critical importance to the continuation of current performance advances in wide-issue and deeply pipelined superscalar microprocessors. In this paper, we propose a new microarchitecture, the asymmetrically banked value-aware register file (AB-VARF), to exploit the prevailing narrow-width register values for low-latency and energy-efficient register file designs. The register bit-widths of different banks in our AB-VARF register files are specifically customized to capture different narrow-width values. Augmented with a value width predictor, the register renaming logic is slightly tuned to rename predicted narrow-width registers to the corresponding narrow-width banks. Our experimental evaluation with SPEC CINT2000 benchmark suite shows that AB-VARF reduces the energy consumption by 78.4% over a conventional register file, on the average, at the cost of a 0.7% performance loss to an ideal 1-cycle monolithic register file. © 2007 Elsevier B.V. All rights reserved.

Identifier

43549107706 (Scopus)

Publication Title

Microprocessors and Microsystems

External Full Text Location

https://doi.org/10.1016/j.micpro.2007.10.004

ISSN

01419331

First Page

171

Last Page

182

Issue

3

Volume

32

This document is currently not available here.

Share

COinS