Low voltage SILC analysis for high-k/metal gate dielectrics

Document Type

Conference Proceeding

Publication Date

1-1-2009

Abstract

Conduction behavior of multi-layer structure of metal/high-k/interfacial layer gate stacks was investigated before and after constant voltage stress. It was found that stress-induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-S1LC) was analyzed systematically with gate stacks of different interfacial layer thicknesses and SiO2-only devices of identical processing condition. Based on the results of defect generation sensed by the LV-SILC, it is observed that discrete levels of trap generation in the interfacial layer primarily causes low voltage SILC in metal/high-k gate stacks and initiates the gate stack breakdown.

Identifier

74949122579 (Scopus)

ISBN

[9781566777094, 9781607680598]

Publication Title

Ecs Transactions

External Full Text Location

https://doi.org/10.1149/1.3118955

e-ISSN

19386737

ISSN

19385862

First Page

283

Last Page

287

Issue

1

Volume

19

This document is currently not available here.

Share

COinS