Electrical characterization of metal gate/high-k dielectrics on GaAs substrate

Document Type

Conference Proceeding

Publication Date

1-1-2009

Abstract

This paper investigates the electrical characteristics at low temperatures through C-V, I-V and conductance measurements to understand the interface trap density behavior of Ti-Au/HfO2/p-GaAs gate stack. Room temperature interface state density, At, estimated for as-deposited Ti-Au/HfO 2/GaAs capacitors was found to be 3.68×1011cm -2eV-1. Low temperature measurement suggests that only fast interface states contribute to the conduction process. Devices subjected to a post-metal annealing at 90°C degraded further. When the characteristics of two different metal gates were compared, the accumulation capacitance density observed to be 1.4 fF/μm2 and 8.98 fF/μm2 for Be-Au/HfO2/GaAs and Ti-Au/HfO2/GaAs respectively at 1 MHz. After annealing, the value of capacitance density decreased significantly mainly because of reduction in dielectric constant. © The Electrochemical Society.

Identifier

63149124882 (Scopus)

ISBN

[9781566776516]

Publication Title

Ecs Transactions

External Full Text Location

https://doi.org/10.1149/1.2981621

e-ISSN

19386737

ISSN

19385862

First Page

455

Last Page

461

Issue

5

Volume

16

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