A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks

Document Type

Article

Publication Date

1-1-2024

Abstract

In this work, a high-speed and energy-efficient comparator-based Near-Sensor Local Binary Pattern accelerator architecture (NS-LBP) is proposed to execute a novel local binary pattern deep neural network. First, inspired by recent LBP networks, we design an approximate, hardware-oriented, and multiply-accumulate (MAC)-free network named Ap-LBP for efficient feature extraction, further reducing the computation complexity. Then, we develop NS-LBP as a processing-in-SRAM unit and a parallel in-memory LBP algorithm to process images near the sensor in a cache, remarkably reducing the power consumption of data transmission to an off-chip processor. Our circuit-to-application co-simulation results on MNIST and SVHN datasets demonstrate minor accuracy degradation compared to baseline CNN and LBP-network models, while NS-LBP achieves 1.25 GHz and an energy-efficiency of 37.4 TOPS/W. NS-LBP reduces energy consumption by 2.2× and execution time by a factor of 4× compared to the best recent LBP-based networks.

Identifier

85162635288 (Scopus)

Publication Title

IEEE Transactions on Emerging Topics in Computing

External Full Text Location

https://doi.org/10.1109/TETC.2023.3285493

e-ISSN

21686750

First Page

73

Last Page

83

Issue

1

Volume

12

Grant

2228028

Fund Ref

National Science Foundation

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