Date of Award

Spring 2007

Document Type


Degree Name

Doctor of Philosophy in Electrical Engineering - (Ph.D.)


Electrical and Computer Engineering

First Advisor

Durgamadhab Misra

Second Advisor

A. S. Kumar

Third Advisor

Leonid Tsybeskov

Fourth Advisor

Marek Sosnowski

Fifth Advisor

Anthony Fiory

Sixth Advisor

N. M. Ravindra


Hafnium-silicate based oxides are among the leading candidates to be included into the first generation of high-Κ gate stacks in nano-scale CMOS technology because of their distinct advantages as far as thermal stability, leakage characteristics, threshold stability and low mobility degradation are concerned. Their reliability, which is limited by trapping at pre-existing and stress induced defects, remains to be a major concern.

Energy levels of electrically active ionic defects within the thick high-Κ have been experimentally observed in the context of MOS band diagram for the first time in Hf-silicate gate stacks from low temperature and leakage measurements. Excellent match between experimental and calculated defect levels shows that bulk O vacancies are probably responsible for electron trapping at both shallow and deep levels. Their role in trapping and transport under different gate polarity and band bending conditions has been determined. For gate injection, electron transport through mid-gap states dominates, which leads to slow transient trapping at deep levels. Under substrate injection field and temperature dependent transport through conduction-edge shallow levels or trap-assisted tunneling due to negative- U transition occurs depending on bias condition. The former gives rise to fast transient trapping, whereas the latter is responsible for slow transient trapping.

Mixed degradation, due to trapping of both electrons and holes in the trap levels within the bulk high-K, was observed under constant voltage stress (CVS) applied on n-channel MOS capacitors with negative bias condition. Mixed degradation resulted in turn-around effect in flat-band voltage shift (ΔFB) with respect to stress time. Under CVS with positive bias, applied on nMOSFETs, lateral distribution of trapped charges in the deep levels causes turn-around effect in threshold voltage shift (ΔVT) with respect to stress levels.

For the incident carrier energies above the calculated 0 vacancy formation threshold and thick high-Κ layer, both flatband voltage shift, due to electron trapping at the deep levels, and increase in leakage current during stress follow tn(n ≈ 0.4) power-law dependence under substrate hot electron injection. Negative-U transitions to deep levels are shown to be responsible for the strong correlation between slow transient trapping and trap assisted tunneling.

As far as negative bias temperature instability, NBTI effects on pMOSFETs is concerned, ΔVT is due to the mixed degradation within the bulk high-Κ for low bias conditions. For moderately high bias, ΔVT shows an excellent match with that of SiO, based devices, which is explained by reaction-diffusion (R-D) model of NBTL. Under high bias condition at elevated temperatures, due to high Si-H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

Time-zero dielectric breakdown (TZBD) characteristics of TiN/HfO2 based gate stacks show that thickness and growth conditions significantly affect the BD field of IL. For the thin high-w layers, BD of IL triggers BD of the gate stack. Otherwise, BD of high-w layer initiates it. During time dependent dielectric breakdown, TDDB, four regimes of degradation are observed under CVS with high gate bias conditions: (i) charge trapping/defect generation, (ii) soft breakdown (SBD), (iii) progressive breakdown and (iv) hard breakdown (HBD). Activation energy of bond-breakage, found from Arrhenius plots of 63% failure value of TBD, shows that IL degradation triggers gate stacks BD, and the wear-out during TDDB.