Date of Award

Spring 1997

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Electrical Engineering - (Ph.D.)

Department

Electrical and Computer Engineering

First Advisor

William N. Carr

Second Advisor

Roy H. Cornely

Third Advisor

Edip Niver

Fourth Advisor

N. M. Ravindra

Fifth Advisor

Conor Rafferty

Sixth Advisor

Guang Yang

Seventh Advisor

Eric R. Fossum

Abstract

The primary objective of this work was to demonstrate the feasibility of an image sensor that is capable of capturing images at 107 frames per second. Such high frame rate operation is based on storage of a certain (N) number of frames into the BCCD memory registers and readout at a slower rate at the end of the frame collection period. To accommodate an optical frame time of 100ns, a high-speed virtual-gate photodetector with six multiple n-type implants was proposed and a novel design strategy was developed. The feasibility of this design was demonstrated by simulating the entire photodetector readout operation using optimized parameters.

A novel contribution in this research is the application of the channel widening effect in the design which reduced the transit time of carriers in the photodetector by a factor of two. The proposed unique geometry was applied to the last implant region by gradually widening the layout design of this section. Extensive 2D simulations were carried out to account for the 3D effects and results were presented.

Another main objective of this research was the characterization of the 3-phase BCCD memory registers in order to obtain higher charge handling capacity. Both 2D and 3D simulations were performed and compared with the available experimental results. The influence of the major factors affecting the charge handling capacity were investigated in detail. The effect of the reduction in channel length was demonstrated by 2D device simulations. Additionally, 3D device simulations showed that a correction in effective channel width adds linearly to the 2D results. The simulations indicated that a key limiting factor on the charge handling capacity was the overetch of the silicon nitride gate dielectric layer during formation of the polysilicon gate electrodes.

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