Date of Award

Spring 1996

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Electrical Engineering - (Ph.D.)

Department

Electrical and Computer Engineering

First Advisor

Walter F. Kosonocky

Second Advisor

Roy H. Cornely

Third Advisor

Durgamadhab Misra

Fourth Advisor

Kenneth Rudolph Farmer

Fifth Advisor

Conor Rafferty

Sixth Advisor

Vipulkumar Patel

Abstract

A process was developed for fabrication of 360x360-element Very High Frame Rate (VHFR) burst-image sensor on the bases of one-dimensional (1-D) and two-dimensional (2-D) device and process simulations using SUPREM III, SUPREM IV, PISCES IIB and ISE-TCAD software, and the process data provided by the David Sarnoff Research Center. This process includes SiO2-Si3N4 gate dielectric, four-levels of polysilicon, three-levels of metal, eight implants, and requires twenty-one mask levels. The imagers with a 2-cmx2-cm chip size were fabricated at the David Sarnoff Research Center. The VHFR burst-image sensor is capable of capturing images at frame rates up to 106 frames/sec. It stores continuously the last 30 image frames at the CCD pixel memory and reads out the detected frames at a slow rate.

1-D and 2-D simulation study is presented for optimization of the charge handling capacity of the buried-channel CCD (BCCD) pixel memory elements and simulation results are compared with the experimental data.

A new concept was developed and demonstrated for large high-speed photodetector with complete charge readout in less than 0.1 μsec. The high-speed photodetector is in the form of a graded three-potential-level pinned-buried BCCD structure. The simulation results of the 33-μm long photodetector of the VHFR burst-image sensor showed that a complete charge read out can be achieved in less than 0.1 μsec. Frame-to-frame image lag of less than 1.0% was demonstrated for operation of the imager with frame integration time of 1.0 μsec for optical test pattern illuminated by 0.4 μsec LED pluses.

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